An active matrix liquid crystal display device or an organic EL (Electro Luminescence) display device generally includes: a substrate on which a thin film transistor (Thin Film Transistor; hereinafter referred to as “TFT”) is formed as a switching element for each pixel (hereinafter referred to as “a TFT substrate”; a counter substrate on which a counter electrode, a color filter, and the like are formed; and an optical modulation layer such as a liquid crystal layer disposed between the TFT substrate and the counter substrate.
On the TFT substrate, a plurality of source lines, a plurality of gate lines, a plurality of TFTs respectively disposed at the crossings thereof, a pixel electrode for applying a voltage across the optical modulation layer such as the liquid crystal layer, a storage capacitor line and a storage capacitor electrode, and the like are formed.
The configuration of the TFT substrate is disclosed, for example, in Patent Document 1. Hereinafter, with reference to the drawings, the configuration of the TFT substrate disclosed in Patent Document 1 will be described.
FIG. 29(a) is a schematic plan view generally showing the TFT substrate, and FIG. 29(b) is an enlarged plan view showing one of the pixels in the TFT substrate. FIG. 30 is a sectional view of a TFT and a terminal portion in a semiconductor device shown in FIG. 29.
As shown in FIG. 29(a), the TFT substrate has a plurality of gate lines 2016 and a plurality of source lines 2017. Respective regions enclosed by these lines 2016 and 2017 constitute “pixels”. In an area 2040 excluding the area in which the pixels are formed (a display area) of the TFT substrate, a plurality of connecting portions 2041 for connecting the plurality of gate lines 2016 and source lines 2017 to a driving circuit, respectively, are disposed. Each connecting portion 2041 constitutes a terminal portion for the connection to external lines.
As shown in FIG. 29(b) and FIG. 30, a pixel electrode 2020 is provided so as to cover respective regions 2021 which will be pixels. In each region 2021, a TFT is formed. The TFT includes a gate electrode G, gate insulating films 2025 and 2026 which covers the gate electrode G, a semiconductor layer 2019 disposed on the gate insulating film 2026, and a source electrode S and a drain electrode D connected respectively to end portions of the semiconductor layer 2019. The TFT is covered with a protecting film 2028. An interlayer insulating film 2029 is formed between the protecting film 2028 and the pixel electrode 2020. The source electrode S of the TFT is connected to a source line 2017, and the gate electrode G is connected to a gate line 2016. The drain electrode D is connected to the pixel electrode 2020 in a contact hole 2030.
A storage capacitor line 2018 is formed in parallel to the gate line 2016. The storage capacitor line 2018 is connected to a storage capacitor. Herein the storage capacitor is constituted by a storage capacitor electrode 2018b formed from the same conductive film as the drain electrode, a storage capacitor electrode 2018a formed from the same conductive film as the gate line, and a gate insulating film 2026 positioned between them.
On the connecting portion 2041 extending from each of the gate lines 2016 and the source lines 2017, the gate insulating films 2025 and 2026 and the protecting film 2028 are not formed, but a connecting line 2044 is formed so as to be in contact with the upper surface of the connecting portion 2041. With such a configuration, electric connection between the connecting portion 2041 and the connecting line 2044 is ensured.
As shown in FIG. 30, in a liquid crystal display device, a TFT substrate is disposed so as to be opposed to a substrate 2014 on which a counter electrode and a color filter are formed with a liquid crystal layer 2015 interposed therebetween.
When such a TFT substrate is produced, it is preferred that a region 2021 which will be a pixel (also referred to as “a pixel portion”) and a terminal portion are formed by a common process, so as to suppress the increases in the number of masks and in the number of process steps.
In order to produce the above-mentioned TFT substrate, it is necessary to perform the etching of a portion positioned in a terminal arranging area 2040 of the gate insulating films 2025 and 2026 and the protecting film 2028 and a portion positioned in a region in which the storage capacitor is formed of the gate insulating film 2025 and the insulating film 2028. Patent Document 1 discloses that an interlayer insulating film 2029 is formed by using an organic insulating film, and by using the film as a mask, these insulating films 2025, 2026, and 2028 are etched.
Recently, it is proposed that, instead of the silicon semiconductor film, an oxide semiconductor film such as zinc oxide is used for forming a channel layer of a TFT. Such a TFT is referred to as “an oxide semiconductor TFT”. Since the oxide semiconductor has higher mobility than amorphous silicon, the oxide semiconductor TFT can operate at higher speed than the amorphous silicon TFT. The oxide semiconductor film is formed by a process which is simpler and easier than a polycrystalline silicon film, so that it can be applied to a device which is required to have a larger area.
Patent Document 2 discloses an example of a semiconductor device provided with an oxide semiconductor TFT of inverted stagger type. FIG. 22 of this document depicts that, on the source and drain electrodes of the oxide semiconductor TFT, an insulating layer is formed by sputtering, SOG, spin coating, or other techniques.
Patent Document 3 discloses an example of an oxide semiconductor TFT of inverted staggered type. The document describes that the semiconductor is oxidized by forming a liquid oxidizer material “self-assembled monolayer (SAM)” on the channel layer of the oxide semiconductor.
Patent Document 4 discloses an example of an oxide semiconductor TFT of staggered type. In this example, the channel layer and the source and drain electrodes are covered with a protecting layer of SiNx, SiO2, or an organic matter.